The present invention relates to a parallel-to-serial converting circuit which converts parallel input data into serial data and outputs the serial data.
The demand for a high-speed semiconductor memory device is increasing more and more, but there are physical limitations on the access time of a core area (memory cell array area) of a semiconductor memory device. Therefore, the semiconductor memory device overcomes the physical limitations on the core area by using a method of processing data in parallel internally, serializing data upon data input/output and inputting/outputting it at a high speed. Thus, the semiconductor memory device uses a parallel-to-serial converting circuit for converting internally parallel processed data into serial data and outputting it.
FIGS. 1 and 2 are circuit diagrams showing the configuration of a conventional parallel-to-serial converting circuit, in which FIG. 1 illustrates a circuit which converts data at a ratio of 4:1 and FIG. 2 illustrates a circuit which converts data at a ratio of 8:1.
As shown in the drawings, theses conventional parallel-to-serial converting circuits include pull-up drivers 110 and 210 and a plurality of pull-down drivers 121 to 124 and 221 to 228, respectively.
The pull-up drivers 110 and 210 always pull-up a drive node A while an enable signal ENABLE is activated to ‘low’. Since the enable signal ENABLE is a signal which is always kept at ‘low’ state during the operation of the parallel-to-serial converting circuit, it can be regarded that the pull-up drivers 110 and 210 always pull-up the drive node A.
The pull-down drivers 121 to 124 and 221 to 228 pull-down the drive node A in response to data DATA<0:3> and DATA<0:7>. When the data DATA<0:3> and the DATA<0:7> have a ‘high’ value, the pull-down drivers 121 to 124 and 221 to 228 pull-down the drive node A; and when the data have ‘low’ value, the pull-down drivers 121 to 124 and 221 to 228 do not pull-down the drive node A. All of the data DATA<0:3> and the DATA<0:7> have their respective active intervals that do not overlap each other. The active intervals have a value of ‘high’ or ‘low’ depending on a logic value of data, while inactive intervals always have a ‘low’ value regardless of a logic value of data. Therefore, it is determined whether or not to drive the pull-down drivers 121 to 124 and 221 to 228 depending on a logic value of data during an interval when the data DATA<0:3> and the DATA<0:7> are activated, and the pull-down drivers are not driven regardless of a logic value of data during an interval when the data DATA<0:3> and the DATA<0:7> are inactivated.
The pull-up drivers 110 and 210 are always driven, and it is determined whether or not to drive the pull-down drivers 121 to 124 and 221 to 228 depending on a logic value of activated data DATA<0:7>. A logic level of the node A becomes ‘high’ during an interval when only the pull-up drivers 110 and 210 are driven, and the logic level of the node A becomes ‘low’ during an interval when the pull-up drivers 110 and 210 and the pull-down drivers 121 to 124 and 221 to 228 are simultaneously driven.
FIG. 3 is a timing diagram describing the operation of FIG. 2.
Eight data DATA<0:7> have their respective active intervals, and have a ‘high’ or low' level depending on a logic level of the data DATA<0:7> only during the active intervals and are fixed to low' level during the inactive intervals. Therefore, the pull-down drivers 221 to 228 are driven during respective different intervals to drive the node A, and thus the eight data DATA<0:7> are serially converted and output to an output node MUX_OUT of the parallel-to-serial converting circuit.
In the above-stated parallel-to-serial converting circuit, a signal of the node A is swung at a level of VDD when the logic level is ‘high’ and at a level of Vth-α (where Vth denotes a turn-on voltage) when the logic level is ‘low’. Because of a structure in which the more parallel data DATA are serially aligned, the larger the number of transistors connected to the node A, the line loading and junction capacitor components of the node A becomes larger, which leads to a problem that a signal of the node A and a signal of the output node MUX_OUT are not fully swung to VDD to Vth-α. Moreover, this problem becomes more serious upon high-speed operation, such as 5 Gbps operation. Consequently, there is a need for a parallel-to-serial converting circuit which minimizes jitter upon high-speed operation and stably outputs data.